I have two nRF9151 Feathers, one is marked v1 and one marked v3. Running the same firmware binary on both, I can’t get the CIPO header pin to change state at all on the v1 board. On the v3 board the identical code toggles it fine.
For this test I put the Feather on a breadboard with a logic analyzer probed directly on the header pins with a common ground. The pins are configured as plain GPIO outputs and toggled from a loop.
Setup
- Circuit Dojo nRF9151 Feather, v1 and v3
- Bare metal Rust (Embassy /
embassy-nrf)
- Logic analyzer on the SCK / COPI / CIPO header pins
The test
Three GPIO outputs toggled at different rates off a 100 ms tick, so each channel identifies itself on the analyzer:
| GPIO | header pin | rate |
|---|
| P0.20 | SCK | 5 Hz |
| P0.21 | COPI | 2.5 Hz |
| P0.22 | CIPO | 1.25 Hz |
let mut clk = Output::new(p.P0_20, Level::Low, OutputDrive::Standard);
let mut copi = Output::new(p.P0_21, Level::Low, OutputDrive::Standard);
let mut cipo = Output::new(p.P0_22, Level::Low, OutputDrive::Standard);
let mut n: u32 = 0;
loop {
let level = |bit: u32| if n & bit != 0 { Level::High } else { Level::Low };
clk.set_level(level(1));
copi.set_level(level(2));
cipo.set_level(level(4));
n = n.wrapping_add(1);
Timer::after_millis(100).await;
}
What I see
- v3 board: all three pins toggle as expected.
- v1 board: P0.20 and P0.21 toggle correctly at 5 Hz and 2.5 Hz. P0.22 never moves, sits at a constant level
Since P0.20 and P0.21 are working in the same capture, from the same loop, on the same board, I don’t think this is a probe, ground, or code issue.
Question
Is the Feather header’s CIPO pin routed to a different GPIO on the earlier board revisions? I’ve seen both P0.20 and P0.19 quoted for SCK in other threads here, which makes me wonder whether the header mapping changed between revisions and whether CIPO moved too.
Or is P0.22 shared with something onboard on v1 that would keep it from driving?
Happy to post captures or try any specific pin if that helps narrow it down.
